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How To Flashing zdr w1
so, welcome to module ten, lecture two, three,so this is on a scan chain base sequential circuit testing. so, if you remember in thelast lecture that is lecture one of module ten, so what we have discuss we discuss thatsequential test circuit testing as compared to a combination circuit testing using thed-algorithm or sensate propagate and justify approach. so, what we have see in case ofcombination circuit you sensitize propagate and justify, so one pattern is enough to dictatea fault, but in case of sequential circuit what we have seen that the basic architectureof a sequential circuit. you have some primary inputs and there isa state register and there is some feedback from that and actually this is call the secondaryinputs or virtual primary inputs, so as this
set up inputs are not directly controllablebecause there output of the state registers. so, you cannot have single test pattern totest the circuit because you require multiple numbers of test patterns to be precise ifthis sequential depth of the number of flip flop circuit is sequence. then, you requirethe sequence number of test patterns to control in the worst case to control in all the secondaryinputs, now once they are controllable, then you can apply the primary inputs at test yourcircuit. similarly, this output of this is also notdirectly observable, so make it to observable directly, so you have to again propagate thevalue through some of the flip flop you take set of another time. so, i mean a so singletest pattern, we have already seen is not
enough to test the sequential circuit by sensatepropagate and justify approach. so, first you have to use the sequence level of numbertest pattern to control the sequence secondary inputs, and then apply primary inputs.so, the sequential number of patterns plus one pattern and the again also with outputpropagate the value the outputs though observe them. so, more than one number that is d sequenceplus 1 or some plus k number test patterns are required to test a sequential circuit.so, you know that wherever we are a going for, what do you called this atpg based testingwith sequence sensate, just a sensitize propagate and justify approach and many times, you canlack to inconsistency, so leading to inconsistency. again, you have to back track, so you assumethat as a sequential circuit testing is order
of complexity of combination circuit testingin to number of test patterns should be applied. so, if you have five things that you havealso discuss on the time frame expansion method that if there d sequence number of depth ofthe sequential flip flop. then, you may required to go to d c minus d sequence to zero levelof time frame that is d sequence number plus one time frames are required to do this.so, you can understand there any last time frame so every step was successful, but inthe last time frame it will be inconsistent. then, whole work is gone and then again youhave to start with a fresh one, so because of this inconsistency today we will see whatwe can do. so, this overall complexity of more than one number of test patterns canbe avoided or can be minimized in sequential
circuit testing. so, effectively what we haveto do, so effectively you have to somehow indirectly or directly control and observethis secondary inputs and secondary outputs respectively if you can do that, then ourproblem is solved. so, let see what will do so as in the introductionwe discussing the major problem of testing of sequential circuit is difficulty in controllingsecondary inputs and difficulty in observing secondary outputs. somehow we have done thatexplicitly or i mean using from other circuit is this is called design for testable or someother arrangements we have to do this. so, that is why we require a sequence of testpattern for atpg of sequential circuit which you want to make it to one kind of a thingso in this lecture what will do will see how
what we can do in this circuit level.so, atpg for combination circuits would suffice for sequential that is somehow we have touse atpg algorithm for sequence combination circuit and do that and say that it is donefor sequential circuit. the part which has to control indirectly we use some other techniquewhich is actually call this scan chain and we will see to control them indirectly.this is this is this is one example of a scan chain design where we in call court concorda simple designs are great. so, if we are doing very complex design, we do a lot offlip flop, lot of gates and all in the very high chances your design is improper or inefficient,but good designs are always simple that is court concord thumb ruling vlsi.if your design is very simple and you are
solve the problem, then you are then you arethe greatest engineer, so great designs are always simple. so, we find out that how thisnight male problem of testing one fault you require the sequence number of patterns totest the sequential circuit was solved by a person who develop a scan chain. the designwas extremely simple, so this is one proof that you can do very elegant design simply.so, actually convert it all the c combination sequential circuit to combinational circuitand then combination circuit atpg algorithm suffice for everything. then, slowly we coulddo away with this sequential test pattern generation with time frames and all and theylast there important and combinational atpg with design for test pattern modify in thecircuit. so, you can directly you can directly
control the secondary inputs and secondaryoutputs observability indirectly using some kind of extra circuit then came into picture.so, for that to achieve that you have to put some extra circuit on the chip which is calleddft, so will be an extra over it. anyway, that extra over it problem is notmuch as will see then compare to the off line headache of for one fall generating this sequencenumber of test patterns. so, how to do that, so one major problem we have seen in the lastlecture was to control the output of the flip flop which is nothing but your secondary inputs.so, how can you do that, so one very simple way of as we already discuss in our lectureswill be using d flip flop as they are standard use in all blss circuits.so, one way how can you indirectly there is
you have to direct indirectly or directlywhat happen, you can see without using explicit test patterns directly, you have to get excessto the flip flop somehow. you have to control them, so indirectly if you want to controlthem, i mean you can you can apply this sequence number of test patterns and go for time frameexpansion. you can do it, but here what we are seeing that that these indirect controlswe want to do it somehow directly where if directly somehow excess all flip flop anddo this. so, you can understand that if you can somehowget hold of the set and reset pins of the flip flop, then you can always what you cancalled take control of the flip flop. we will see an examples if you can directly somehowget excess to the set and reset inputs of
the flip flop. then, you can directly saymake them 0 over 1 and require for the secondary inputs, so if that time we did not go forthis a sequence number of test patterns do make the make this secondary inputs controllableindirectly. so, we can use that, so what is this truth value of the d flip flop you cansay. so, if i make you say reset equal to 0 ifyou say, then you are and set equal to 1 if you set, then you are going to set your flipflop. so, what is the idea input you do not do not care at that time because you directlycontrolling the flip flop the set and reset and clock is also would not require. you willdirectly get the output q s 1 and if you make the reset s 1 and set as 0 and what is goingto happen you will directly get the output
of the flip flop as 0, you did not apply clock.all those things somehow if you can control the set and reset line externally, then youcan directly set this secondary inputs as you require and for the set and reset is notallowed. it is the illegal condition, but now if youwant to operate normally on your flip flop then you set make reset equal to 0 this oneand if we apply a 1 sorry if we apply a 1 when you set and reset a 0, we apply a clockage. the next stage you will get one those d flip flop you apply a 1, then you applya clock age your set and reset should be 0 at the time and next clock age will get a1 and 0. for the same case, we give input is 0 and apply a clock first your set andreset should be 0, the output will be a 0
is a normal operation our flip flop.if you want to directly, but not if you want to the clock first to control this flip flop,then you know that this is input there will be lot of combinational clouds, there willbe angle set of the flip flop here. so, you require the sequence number of test patternsto if set this inputs, so that you get the design base output as this one, so if youwant to get a 0 over here, indirectly you have to set a 0 here. for that, you may haveto conclude this flip flop and so which you require d sequence number of patterns. now, if you somehow control this and this,then directly you may reset equal to 1 and the set equal to 1 you do not if it any itapply a clock first and you will get the output
as 0 which is required. so, let us see whatwe what you gain this you can directly do this, so if it remember by last lecture wesaid that this is the circuit. you can think that the set and reset lines were not there,so the idea was we are asking can you test this fault, then you find out that the setand reset lines are not there, it was in the question and answer session in last lecture.then, we found that this fault cannot be tested because you know that the how this outputis react this output is x kind of a thing and for this stuck at 1. we have to applya 0 and if you know that this is 0 slash 1 and in the case of xor gate this output willbe xor x prime because x was 0 in case of xor gate output is the output is whateveris the input here will be the output.
you can apply a 1 over this for this is afault this x is become x prime, so it will be x and x prime, so never you can get anycomplete value and you cannot able test your circuit. so, that was the case, now we cansee that use of the set and reset lines you have, then what can you do, so for examplewe know that all the lines are x for the time being, so this is the x, this is the x, thisis the x. so, what we will do, so what we can do that,now we can we have a direct excess with flip flop, so you make set equal to 1 and resetequal to 0. so, what it to wants to do, so without apply in the clock also you have thisoutput will be a 1 this is the output 1 and this output is the one because we have setthe flip flop directly using set and reset.
now, this is stuck at 1, so what you can dothat so you have one over here you have one over here, so and now if this is this is yougot just by a, what do you do the first effort you have to done first step you apply setequal to 1 reset equal to 0. so, you get a 1 over here get a 1 over here,now what you do you make set and reset equal to 0, so what will do happen now the d flipflop will be operating in the normal clock mode. now, this is a 1 over here, so whatyou have to do you can apply primary input 0, so normal case zero fault case 1 becausethis because the stuck at for. so, it is a d over d prime over there and we know thatin case of xor gate if the other input is one then the second is prime is inverted.so, you get a d over here know what you have
to do, so this you make 0, now what we canapply is you apply the clock pulse over here. so, this output will come out of the primaryoutput which will get here and the fault is tested as now become testable when you areusing a line. so, this solves the great deal of problem that some of the faults which areun testable if you considered your circuit without the flip flop, sorry without the setand reset know became testable secondly one more thing is there. so, that again we willsee in the other example, so what are the advantages of controllability and observableof flip flop with what you call this. a fault which was un-testable by the timeframe expansion method last lecture is now becoming testable using the set reset flipflop that is why so secondly. so, what we
have seen is that e, now only one patternwe will see only one pattern is required to set and reset the flip flop and propagatethe effect to the output. so, the idea is there if you look at it so only one patternthat is actually that you can call this set equal to 1 and the set equal to 0 that isone pattern will which will set the flip flops. if there more number of flip flop for allof them we have to set and reset is required and there only one pattern will dry your answerto this one. so, indirectly what you are going have ifyou set and reset lines in your flip flops one pattern is required to set and reset theflip flop as required for your secondary inputs and secondary output kind of a thing. secondaryinput controllability you can directly get
by setting as the resetting the flip flopsdirectly by the set reset pins and now one pattern is required to be applied which willsensitize the faults and propagate the value to the some flip flop kind of a thing. now,instead of these sequence patterns to initialize the flip flop you can have, so unlike timeframe expansion where you require d sequence minus 1 patterns required to what you callsensitize propagate in justify. so, in this case only one pattern is solvingthe problem or you can call 2, only 2, basically to set the reset of the flip flop and 1 toactually sensitize the fault effect that is by the combinational test pattern. i willget that is this pattern, actually this is you are applying a 1 0 over here. so, thispattern is by combination atpg and the other
set reset you are doing by this, sorry thisset you are making as 1 and 0 this is the other test pattern, so two patterns are requiredto solve your problem. so, these actually says the number of patternsand also the test time, so what we have done by using the set and reset lines we have solvedone problem. we have actually going towards combination, i will got to test sequentialcircuit, now instead of using this sequence plus one or another of this sequence numberof test patterns to set the secondary inputs. then, what we are doing then again we arecoming back to applying this d i will got the final pattern to do it. now, we are youcontrolling now instead of the order of the sequence of test patterns, what we are doinghere.
now, we directly controlling the flip flopoutputs that are the secondary inputs, sorry the secondary outputs by rightly setting orresetting flip flop inputs reset or set likes of the flip flops. now, you can directly givethe pattern required to test the faults, so we have rustically change the order to 2 fromthe order d sequence plus 1 to order of 2 so this is the very he very great help andslowly we are going to a prime. we are converting a sequential circuit toa vertical combination circuit for testing and applying combinational test pattern. iam solving the problem now that for a simple example last example, now we will go backdo the big example which you have considered in last lecture. so, if you remember thiswas our circuit this was our fault and they
were two flip flop, if you remember, so whenwe will done d, i will go on there, so we have found out that we require a 1 over here.also, we require a 1 over here to test the faults because 0, so you require a 1 overhere and also you require a 1 over here. so, if we are applying 1, 1 here, so you willget a 0 over here, so the effect is d over here and this effect will be d over here.so, make a 1 you require a 1 over here, so this also one over here something like thisand this was the scenario if you look by the last lecture you will understand. now, themain issue was here that we are how can we in this this was the secondary input as wellas this was actually another secondary input. so, because this is the output of the flipflop somehow how can we indirectly control
this, so in this case in the last lecturewe have seen. we apply a 1 we applied a clock pulse whenthe value came over here after that we applied a 1 over here and this one was already there.we applied another clock pulse the one came here and again this for the same thing thisone was retained. so, this one again has to be transferred over here, so all this we havediscussed, but we require two patterns to set an this some to arrange to get a 1 anda 1 over here required to test patterns first it was a 1 over here c equal to 1 was here.so, if you see c equal to 1 was required and a clock pulse then b equal to 1 and c equalto 1 we required so said this flip flop sorry this flip flop output and then finally, aequal to 1 and b equal to 1. we applied to
test this fault, so three patterns were requiredto test the fault so d sequence of the circuit equals 2 that we have already seen. now, letus see how can we reduce this by using set and reset line of flip flops, now you knowthat we require a 1 over here we require 1 over here. so, now instead of going for time frame andactually doing for a clock pulse what we will do we will make this one as 1 and this oneas 0. so, immediately you do that, you get the output as 1 because it will set the flipflop for the same thing for the other flip flop. also, you make set equal to 1 and youset equal to 0, immediately you get a 1, now your job is done, so you get a 1 over hereand 1 over here.
so, what we are doing only two patterns arerequires doing this one pattern to set the flip flop and another pattern to test it.so, you make this and this, so this output and this one are set, now what do you do,so you note you get a 1 and a 1 by resetting this. now, we have to again go for the normaloperations of the flip flop, so you make them 0 as 0. so, that is the normal operation isdone, now you make z equal to 1 b equal to 1, so if you do that you will get a 1 overhere and this will be a 0 over here. so, this will be 0 this will be one is the1 over here and a 1 over here for the and gate, so you will get a 1 you will get a das shown where a d has to get a 0 and your job is done. so, you require two test patterns,one is one is to set the flip flop this and
this because the 2 a b x are not a b c arenot important. so, you said this to flip flops then in thenext pattern, you go you just apply this patterns and your job is done. so, you have to rememberthat if you can have 10,000 flip flops, only two patterns are required to solve the problem. one pattern will be to set and reset the flipflops the other pattern will be for what the other pattern will be just if you can seeeven if you have another ten flip flops. if you just think about that if you have anotherten set of flip flops, then also you did not worry why you need not worry because in caseof time frame expansion method what was happening. if you have some something, let us again seeback what we are doing, so if you have you
have to observed that it is, so you can thinkthat that is a small circuit, so all it to flip flop, so here we are required two patterns.the idea was not that the idea is if it in your 10,000 flip flops, again two patternsare required to solve the problem say for example, you have some 10,000 flip flop someother stuff is there. so, if you are using time frame expansion method, then one patternwill be required to set this another pattern, it will be required to set this another patternwill be required to set. so, if you have 10,000 flip flops in sequence, so if you d sequenceis equal to 10,000 and then you are in a big problem.so, if you have a 10,000 flip flops in the sequence you require the 10,000 patterns tosolve the problem set the primary outputs
of the flip flop primary outputs of flip flopsare nothing but they are your secondary inputs. so, you have to do that and then one patternwill be applied here to test the circuits, but know you see if you are having directaccess to the set and reset lines. then, what you can do one pattern if you want a 1 overhere you make set equal to 1 reset set 0 if you set 0 over here make set equal to 0 andreset equal to 1. similarly, if you want again get 0 over here and reset equal to sorry setequal to 0 and reset equal to 1 and all these things.you want to have you can apply; finally these are all the flips of individually controllevel that we have to assume. then, your problem is solved, so two patterns are done for thisone, no you see what you see and what you
gain and what you lose, so gain is only twopattern two pattern to test the circuits. if as the number of flip flops are there whatmay be or may be the sequential depth and need not worry at all your job is done. onlytwo patterns are required for this one, but most important point is irrespective of thevalue of the sequence only two patterns are required to test the sequential circuits.so, that is the greatest boon you are getting that you have converted a circuit from a sequentialcircuit your virtual combination circuit and you are solving your problem. so, d algorithmis doing everything for you need not go for time frame expansion all this, but if youlook at those black diagram of the circuit. so, we are at just look at the block diagramso these are a b c with the primary inputs
primary output is there and such at one toset lines for flip flops and to reset line put to then a clock if you think that i have10,00 flip flop. then, what will be case this will be the primaryinputs this is your output and this will be your clock and how many set lines will bethere 10,000 set lines will be there for 10,000 flip flops and 10,000 resets lines will bethere for the 10,000. these are the set lines and these are the reset lines, so know youcan see the complexity, so 10,000 set lines and 10,000 reset lines are there to do yourproblem. you can understand that maximum number of output of a primary input output of a chipcan be maximum 1024 or something like that 512.they are very expensive to get a package like
this where you can have 512 for 1024 inputs,now if you have 20,000 inputs such packages are not available and you cannot do a circuitlike this. so, we have gone one step we have converted a circuit to a virtual combinationalcircuit and we have solve the problem and now the night may have again started thatthis set and reset lines are too many in number. so, how can we do that then the engine isstarted to solving the problem, so we cannot have we will use the concept of having a setline or reset line we will control them, but how can we control them by bringing them.so, many pin outs, so bringing many pin outs is not fusible because you do not have packageor packages means anything which you have seen in the second year classes. you haveseen the digital of the black packages are
there. this called the dip, dual inline package,so their silver pins and all, so how many we have seen we have seen around 1024 or maybe 30 or 40. you might have seen for this, but 10,000 or20,000 is almost impossible and it is not doable at all and also that is an also yourequire a net is so we have also this is verity in the very first lecture of this testingmodule. so, you have to require 10,000 plus or 20,000 of the 80 which is also a very expensiveequipment and that the number of probes to give inputs to the 20,000 fees is also notfees able, so that idea is dropped. so, now what we will have done they are sayingat atpg set and reset by shift register now the problem they have found out was you inthe same example you are going to check. so,
you required a 1 over here and you requireda 1 over here that was the requirement, so for that you have to make set equal to 1 setequal to 0 set equal to 1 and set equal to 0 that was a requirement if you remember.now, what problem we had the problem is that if you want to bring this pin, four pins,so 10,000 probe means 20,000 pin out should be there. then, how to do this so people havesay that we cannot have that many bring outs, so how can we solve some people give the ideathat we use what is called a shift register base technique. now, what are the shift registerbase techniques, so in this case the we just want to minimize the pin outs, so we willhave a set of what you called another shade set of register. the set of flip flops whichis in a connected in a what do you call a
shift register kind of thing.so, 1, 2, 3, 4, so there are four pin outs, so you have if there n flip flops, so yourequire 2 n number of scan what we can called shift register 2 n flops in shift registeris the idea. so, 4, so here will be 4 or if there 8 flip flops, so there are in the 16in this case so that will be that is the idea. now, what you do so that is the problem youare having, now what they have done, they have saying that now instead of bringing thispin out, there will be connected this, so the output of each pin of a shift register.so, you now see you have two flip flops so i will put a shift register of four flip flops,so if there are 5 or 4 flip flops in the names of the i will have 8. now, the first outputof the flip flops for this shift register
will be connect to the set line the secondflip flop of will be connected to the reset line. similarly, the third output of the shiftregister will be connected to the set line of the second flip flops and last flip flopoutput will be connected to the input of the reset input this second flip flops. so, nowwhat do you do, sorry now what you require the connection is done.now, you need a 1 over here, a 0 over here a 1 over here and a 0 over here, now whatyou have to do you can say that this you require a 1 at the output here 0 here, 1 here, 0 herebecause now this input a set and reset lines we are driving externally from anything. so,you are not driving by pins, so if you look at the last lecture last slide if you seeso there were external pins there were external
pins and you put apply them parallels. itis in one go you can apply all this flip flops in one go, but for that you can set and resetthe flip flops, but for that what do you require you require there are the circuit or thischip design or the chip packaging plus 20,000 input output like this.so, that is, sorry input like 20,000 that is extremely difficult problem, but in onego you could have control all the flip flops outputs directly in one parallel. now, inthis case you require 1, 0, 1, 0, now you know that in shift registered in one go youcannot have one 0, 1, 0 you cannot have directly in shot you cannot having. so, what you haveto do you have to apply 1, then apply a clock pulse then 0, then apply let us see how itwill happen, so you required four iterations
to do this.so, first you apply a 0 over here, so this is the requirement, so do not go about thisthis is the requirement you can think. so, you will requiring the end, so first you applya 0 give a clock pulse, so the 0 will come over here. now, you apply a 1 over here a1 over here now you apply a 1 over here you apply 1 over here and your premium, but thenall these clocks are same and this clocks are different. these are the important toknow this is circuit clock and this is the shift register clock two clocks are now cominginto picture, now you give a 0, now you give a 1 another clock pulse you have to all this.so, now this 0 will be coming over here, so will give the 0 over here and this one willbe here, now you get a 1 over here and a 0
over here these are all actually do not caresnow you do not know what is gave you they not credit. now, you give another 0 over hereand give a clock pulse, sorry you give another clock pulse over here, now if you give a clockpulse what is going to happen the 0 will be here. so, this will be a 0 over here and thisone come over here this 1 come over here and this 0 will go over here, so this will bethe case. now, in the n you apply a 1 here and givea clock pulse, so once you do that, so this zero will come here this one will be cominghere this 0 will be coming over here and this one will be coming over here.now, you have one zero one zero which was require so you require 0 clock pulse 1 clockpulse zero clock pulse 1 clock pulse. so,
four clock pulses are required in this caseto shift your value require to control n to control the input and the set and reset improvethe three clocks. now, you can say that so if you have say 10,000 flip flops, now whatis the case you require 20,000 clock pulses to control this flip flops the answer is correctlet me have to do and also you have seen that you are a t a time is very expensive. youcannot have a, you take this type of 20,000 input times you cannot have or it is veryrestrictive to do it, but now this problem. they have found out that this problem stillremains if you look at a sequential circuit tested this problem people have not be nearto solve as of now to minimize the test the this number of clock patterns to take thepart. somehow they are using fault collapsing
because you have already seen that fault collapsingalgorithm. so, minimize the number of faults only thosethings, they will be doing minimize the number of faults, but this shift filling of the shiftregister will see this scan chain the modulate person of this. that will be seeing in thenext, but any way 20,000 of pattern or whatever to said this flips to set and reset linesindirectly or means what we called in an implicit manner cannot be there.so, this number of test pattern clock periods will be required shift the pattern here whichcan indirectly directly get access to set and reset line and control the output of theflip flops, but here is the problem here a 1 advantage, did you solving the problem.so, this is the clock for the circuit and
this is the clock for this this s clock isthe clock for this shift register. now, this two clocks are keep different, now why itis the idea here is that if you look at these clock pulse, so this clock pulse so this clockpulse is arriving on a drive gate and this again the output is driving another what youcall inverter then another data. so, whenever you get the data whenever thisclock pulse comes, the data comes over here so they application of the clock pulse withdata will come here say it will take some time for the propagate take over here. so,you cannot have a very fast clock over this period because whenever you apply the clockpulse your data will come here then to get the data here. we can assume that the anotherflip flop over here to then this data this
data the change in data should be arrivingover here, then only you can use another clock to figure this flip flop use the q.so, this is the long path, so this output is there end gate is there then inverter isthere then the or gate is there, then the date will come, so there were some dealingof the data traveling from here to another flip flop input. so, this clock period hasa limitation in speed you cannot go for a very high speed clock over here say of thisis the slow clock, but if you have this is the safe register. so, this output is connectedhere, this output is connected input and so far there is no gates here no gate here andno gate here directly you can fill it, so there is no dealing.so, once you have by the clock the clock comes
and there is the data comes and immediatelydata gave transfer to this input of the data because had they are been a lot of combinationalcloud over here. then, you would have to wait from this data to becoming from here to herethen only you can apply another clock pulse. now, this is not the case here the outputis directly connected from this to this the output is directly connected from this tothis. so, your problem is solved so you can applya very first clock over here compare to this clock so that you this fill up this fillingup can be done in a very fast gate. so, even you have to say for 10,000 s flip flops evenyou have to have 20,000 patterns to set a reset this lines, but then again your problemis not high. if it is say 10 megahertz clock,
so you can use it at 500 megahertz clock orsomething like that. so, usually you can also use a gigahertz clockover here and very quickly shift the data, but this will be slow because there lot ofcombinational dealing in this case. so, the number of test patterns if in case of in thiscase the number of test pattern were two because in one pattern you set and reset all the flipflops in one go. then, we apply the pattern in done it, butin this case the set reset lines have to be filled up in a sequential manner, so numberof test pattern required you can see is that 0, 1, 0 clock 1 clock 0 clock 0 0 clock 1clock that will take around 20,000 cycles if the 10,000 flip flops. that can be donein a very fast rate that can be done in a
very fast rate this way and one more pointyou have to remember over is that. so, you can ask may be that, so 20,000 clocksperiods i mean sorry 20,000 patterns are required 20,000 or a 12 number of the flip flop patternsclock periods are required to shift the data here. so, you can say that if there are nflip flops then 2 n patterns are required to do this to control this set and reset andtools. so, you can also say that the time frame expansionmethod also you are also one more saving the same things. so, if there is a de sequencenumber of flip flops then what you have to do you have to apply in time frame one yousaid some of the flip flop in time frame to use the some flip flop in the de sequencetime frame after de sequence time frame. all
the flip flops are said, then you have appliedthis and you know that this sequence of the number if there are m flip flops. so, here2 n patterns i mean 2 n series are required, but in case of time frame expansion methodonly d sequence number of a pattern said required. you know that the de sequence is del d sequenceis sorry the value de sequence will be less than de sequence to n why because if the allthe flip flows are tide out in one chain like in this case 1, 2, 3, 4 all the flip flopsare tied out in one chain. so, here this sequence will be 4, but if sometimes it may happenthat there are many of the flip flops are in parallel that is not all the flip flopsare dependent on the previous one. so, all your de sequence is the maximum depth of theflip flop that may be equal to or less than
so you can say that these you call these timeframe expansion methods in its time frame. you control some of the flip flop output,so it may not be two ways, two way means actually double the number of flip flops. so, whichis required in case of shift register base testing using same to same then still whyyou are going for this one why you are not going. i mean this one you can call sequentialtime frame expansion the answer to give this sequential time frame expansion method isa very complex term, so what may happen is that in one time frame say d minus de sequenceyou set some of the flip flops. then, in time frame this sequence minus 1plus one you use some of the flip flop, but you are not using this set and reset linesto do that. so, what you are going how you
are setting up or d setting the flip flopsin case of this say means time frame expansion method we are using the primary inputs onlyto do that. so, primary input means you have to get axis with flip flops you have to covesome of the combinational circuit like for example, you are seeing that. so, this isflip flop which just have to be control and there is a lot of combinational circuit overhere, so you have to control these inputs in time frames approach to get an axis tothis one. if you remember this example like in thisexample you say that by using the time frame expansion method you cannot trace the circuitbecause using the primary input output. you cannot control the primary output, but bythis d resistor i mean was you set reset line
you can directly have this control this. youcan test it in other words this this method that is direct axes to the set and reset linesof the flip flop sequence using, so what advantage you are gaining is there is no question ofany inconsistency always you can control the flip flops.so, even you are applying two n number of patterns to set reset and reset lines, butyou are never going to have an any inconsistency, so just to apply d algorithm get the testpattern control the virtual primary inputs by the set and reset lines apply the testpattern. you are done, so it is very simply that incase of time frame expansion methodyou require d sequence number of patterns which is less than 2 n, but at say it is verycomplex in nature. that is you may have what
is the case that you may land up to a bigproblem. in the last time frame before the circuityou get the inconsistency and again you have to re do so that of line complexity is sohigh. that may be left slowly moving towards this what you call this time frame expansionmethod that slowly forgetting and there going for this set reset line sequence. so, youcan see that this is what i was discussing, then how can you trace the circuit, so thispeople have say 1, 0, 1, 0, they have done and they are apply the pattern like 1, 0,1,0 in four clock edges. we have done this one so this is how you dothe testing that means four clock pulses you sated and you then you apply this 1, 1, soin four stages one, sorry there is a let us
have a look at in the steps. so, how you dothat so this is the circuit, so you require 1 over here and a 1 over here so you requirefour clock pulses you shift 1, 0, 1, 0. so, it is 1, 0, 1, 0, you shift it and then yousorry all set are done those how we are apply 2 n number of patterns to do that into twon clock obviously this clock this clock would be much faster than this clock. now, whatyou have to do another problem over here not only 2 n, so more complexity we are adding. so, now all this lines has to be 0 becausenow you want to operate this circuit normally if you want to apply and get this d over here.so, again this four you have to apply by 4 clock pulses, so not only 2 n, so 2 n plus2 n number of clock periods are required to
set this flip flop or reset this flip flopsare required. then, again you have to make everything 0 set 2 set 0, so there is circuitbecomes normal and then you can apply the pattern to do this clock. so, huge numberof extra number of test patterns are require to control the shift resistor to do this setreset controlling and that actually. so, this design was also not very popularand then actually the what do you can call the main design achievement of testing whichis call the most important. if you see that what is the most important design in caseof testing i will say it is the scan chain. so, then this scan chain came into picturewhich actually solve this problem forever, so here will be the partially solve the problemthat there is only two pins testing and test
out there is one separate clock that is onlythree extra pins were require. now, you require two n plus two n number ofclock periods extra to set and we said this shift resistor which are controlling the setand reset lines to get axes, but now but this actually is also taking if there are ten 10,000flip flops. so, you are having 10,000 or 2 if there is it will n we are saying if theren flip flop then two n number of extra flip flops. we have to add and 2 n plus 2 n extraclock periods are required to control this to do this, so that is a big problem whichis give into picture. then, this is our diagram as i said, so ab c are the inputs this is the testing and this is the test out to extra that the shiftresistor input shift resistor output primary
output and two clock. so, additional pin is1, 2 and 3, so 3 in 3 additional pins you can do this, but if there n flip flop 2 nadditional flip flops you add additional flip flop. you require as well as 2 n plus 2 n,it will give four n test pattern to control this shift resistor, so this is the penalty,we have to apply and actually this was solved by a person.then, what will be case this will be the primary inputs this is your output and this will beyour clock and how many set lines will be there 10,000 set lines will be there for 10,000flip flops and 10,000 resets lines will be there for the 10,000. these are the set linesand these are the reset lines, so know you can see the complexity, so 10,000 set linesand 10,000 reset lines are there to do your
problem. you can understand that maximum numberof output of a primary input output of a chip can be maximum 1024 or something like that512. they are very expensive to get a package likethis where you can have 512 for 1024 inputs, now if you have 20,000 inputs such packagesare not available and you cannot do a circuit like this. so, we have gone one step we haveconverted a circuit to a virtual combinational circuit and we have solve the problem andnow the night may have again started that this set and reset lines are too many in number. base technique. now, what is the shift registerbase technique, so in this case the we just there 8 flip flops, so there are in the 16in this case, so that will be that is the
idea. now, what you do so that is the problemyou are having, now what they have done, they at the last lecture last slide if you see,so there were external pins there were external input output like this. in the circuit, but if i make it the modeone then i will take control of this step. so, let us see how it is done, so this theadditional thing i was talking about, so this is your flip flop in before that has input1 multiplexer. so, this is his control for the first flip flop a normal output of thisone and this is be mode, so this is a actually we can call this this block diagram of a scanflip flop. now, what is flip flop of a scan flip flopshere will have normal inputs scanning that
is a special input this is a scan out clockand mode. so, if your mode is equal to 0 the normal input will be flowing in if you havemode equal to 1 then this scanning will be feeding in and that are the two cases. so,this is over scan chain normal inputs scan input clock and the output output is common,this is the block diagram of this one now you see what that has done. so, now you said that i want to take controlof the whole flip flop as i told you, so you may have some inputs like this, so an inverterif you remember, so this one was over inverter. so, there was some and gates over here thereare some also and gates over here this was a short this was c this is from here. now,he says that for some testing you assumed
that a for some testing also you assumed thatthis c as to be a 1 this one as to be a 1 for some fault you required that this as tobe a 1 that is this output because this c is that over here. so, you required this tobe a 1, so for a some reason you want that and other things this input a, this inputb, this is c and this is d. so, you can call that this d is also connectedto this one as this one same case have and you said that you required this to be a 0for some fault testing because assume that is some fault testing. so, how you will do,so what you require in this scan chain. so, what do you require in the flip flop thisoutput you do not require see you required to be one because this is a virtual primaryinput or secondary input thus as to be made
one.so, you require controllability of this and this also you want make it to be a 0 becausethis is connected to this pin which is to be 0. so, how to do that, so if you look atthe old story that is control reset, so what we have to do we have to make this a set equalto 0 reset equal to 1 reset equal to 1. so, this will be 0 this is 1, so set will be onereset will be 0 and here it is do not care do not care about this. so, once it is done,so you will get 0 1 and required that you have to make set equal to 0 reset equal to0 is equal to 0, this is 0. then, the circuit will be normal mode andyou can do that so for but, for that if you see that if the 6 a flops, so what do yourequire. so, six flops you require either
a three flip flops, so either you would requiresix pin outs. so, you require either one, two, three, four, five, six extra pin outsa six extra pin outs you require or whether what do you know or whether we have to usea ship register. so, which will having six flip flop and that line makes your life veryhealth because either extra number of thing say now or extra number of what do you cancall a flip flop, sorry so what this person as done he has put some extra multiplexer.now, we are seeing that already this three flip flop are there in my circuit then whydo you want to additionally incorporate another flip flop chain to do that. so, you said thatwhen you are when you have to get the value of one over here and a 0 over here that wasrequired. so, a d over here, so you was to
do that, so how why you should use anotherextra chain. so, he said that i will make my mode equal to 1, so when mode equal to1. so, this input get connected here these output get connected to here because thisnormal output from the in output from the eraser block is now cut because a all themodes are one. these are flip flop, so this is connectedto this one, now you see automatically a chain has been developed using this is very importantto observe that a chain has been developed not by using any extra flip flops. again,i repeat not by using the any extra flip flops it has been obtained by using the flip flopwhich are already develop already was there in the circuit were addition additionallyadding some extra marks. that is the only
thing is added, now you make mode equal to1, so you get the chain connected now what you have to apply.so, you have to apply a 0, a 1 x and you have to apply, so that why i told you that hasnot been yet solved all that part is not yet solved in the very in matured way that howcan you mean reduce the number of the clock be rates to do the testing. so, in this casethree flip flops would be control, so you apply 0 1 x and you apply three clock pulses.so, initially this 0 will be a x, will be here this will be x will be here x will behere, then you apply a 1. so, you will get one over here x and x overhere x and x over here then we apply another clock pulse kind of a thing, so get the chainset. so, chain can be easily said over you
see some patterns so that will again see someexamples, but in three clock pulses said it, now what you do. so, it is 1 this is, sorrythis is 0 this is one and this is x you required, now what do you do, now again you know thatsome inverters is there some and gate is there something like this. now, you want to test your circuit we areapplying some patterns. so, now what you have to do now again you have to become this chainand make this circuit in the normal mode that is set result board as to be made. so, whatyou can do you just make this mode is equal to 0, so once if mode is equal to 0 will bethere in normal circuit input will be going to the, sorry going to the output somethinginput something flip flops. so, make mode
equal to 1 and normal connection is thereflip flop you can give it, so here what we have achieved. so, this actually the diagram will see whatis there, so this is what is required. so, you can see that this is the secondary inoutputs this is the secondary inputs this we have to actually controlled. so, what thisperson as done, so he has done mode equal to 0 if mode equal to 0 the secondary inputsare directly coming to the circuit. we in this case there is nothing controllingwhen the circuits are operating normally, now in c what you are doing? so, in this caseyou are making mode you make as 1 and then what happens you can get directly controlof this flip flops you can control.
the set whatever value you require you oneand then to come back and make mode equal to 0 then this sanction will be decouple therewill be no change normal circuit will be there, you can apply your test pattern and to thetest state. so, this was over lecture about the scan chain, so next lecture will givesome elaborate example say how what is the advantage and what is the disadvantage? butbefore closing, i will just see one thing that what is the gain we have achieved, sogain we have achieved. now, it if there are n flip flops in the circuitswe do not require 2 n number of flip flops we do not require 4 n number of clocks andpatterns. so, what we require if there are n flip flops we require n mux and it is alreadytwo is to one mux with size or it area is
much mux less than the number of our flop.so, you just require n flip flops, n mux is equal and you require n patterns to set theflip flops, so in last case you require 4 n. now, we require only n and instead of 2n extra flip flops you require just n number of mux. so, we have reached we have reducethe problem a great deal and that actually became the path opening for testing of sequentialcircuits. so, if you say what is the best design whichis possible has been reporting incase of sequential circuit from my opinion i will be saying isthis scan chain. so, now just solve the rod of important problem it as solved like timefrom expansion collisions or inconsistency it as solved secondly what it has solved.secondly, it has solved about your you do
not require 8 of flip flops just you requiren mux with multiplexer 2 is to 1 with sizes must revolt then flip flop.second, you do not require 4 n number of clock period to set or reset you just require nnumber of patterns to set or reset the flip flops and also you have to observe one thingthat here flip flops do not require a set, and a reset line is not required over herewe are doing it in the normal way. so, one of the flip flops size can also be smaller,then the set or reset flip flops. so, that you can a you can incorporate this one insize that you can say that if ever flip flop set and reset signals then it area will belarger than the circuit. then, a flip flop which does not have a setin the set line then you can think that the
mux area you can say that flip flop with lineis almost equivalent, so flip flop with the mux. so, infect this a additional mux is notat all a problem, so additional mux we are adding that n mux area we are also savingby not using any kind of a set reset flip flop. so, that is again another great boonwe are getting correct and only thing it that n number of pattern will be required to dothis. that is only problem that remains and cannot be solved as of now we are just seeingand one more thing is that in case of scan chain.so, this same flip flop you can see and the same clock is there, but this now the clockis operating in to different mode, that you have to know this circuit complex conceptbecause when the circuit is operating in the
normal mode that is in this mode if you cansee the circuit is operating in the normal mode. so, if these is the normal mode is therethen the output of this flip flop is go to this combinational lot of combinational cloudswill be there. again, you can get the output the outputs, so this is a delay, but so yourclock as to be bit low arrange this case, but when you are doing working as scan modethen what is happening this output this is your chain this output is no longer there.so, your flip flops are only in this mode so there is no combinational delay, so youcan use this clock in a very fast rate. so, when you are scanning in the data to set thevalues in the flip flop you can do it very fast rate because there is combinational delaythat much, but when you are in the operating
the circuit in normal mode. so, you have todo it in bits lower rate so that this is combinational delay are matched. so, almost all the problemsare being solved by this scan chain only one problem that remained is that n number ifthere n number of flip flops in the wrist case n number of patterns are require or nnumbers of bits 0 as 1. so, require to control the flip flops to 0and 1, so that is only the problem that remains to be solved. so, in the next lecture on this,what we are going to see we are going to see how we can handle this n clock period business.how can you reduces this is one more and second we can see that what are the other variationsor other advantages we get in scan chain with that we close for the day.thank you.
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